EN0-001 Online Practice Questions and Answers

In the Generic Interrupt Controller (GIC) architecture, which of the following ID numbers are reserved for interrupts that are private to a CPU interface?

A. ID0-ID7

B. ID0-ID15

C. ID0-ID31

D. ID0-ID63

In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)

A. Processor reset

B. Switching from ARM to Thumb state

C. Changing the access permissions of a page

D. Executing a Data Memory Barrier instruction

E. Loading data from an unaligned memory address

Is it possible to use an interrupt controller based on the Generic Interrupt Controller (GIC) architecture in a device built around a single core Cortex-A9 MPCore processor?

A. No, they are completely incompatible

B. Yes, all Cortex-A9 MPCore processors include an integrated GIC

C. Yes, but a dummy second processor has to be included

D. No, a GIC is only compatible with multi-core Cortex-A9 processors

Which TWO of the following mechanisms cause the ARM processor to take an abort? (Choose two)

A. MPU fault

B. External memory system error

C. Bounced coprocessor instruction

D. Unrecognized instruction opcode

E. Illegal operands for a data-processing instruction

A C code segment contains three calls to a function, foobar ().

This code segment is to be linked with a static library that defines foobar ().

Ignoring inlining, how many copies of foobar () will the ARM linker place in the output?

A. None

B. Always one

C. Always three

D. One or more depending on optimization level

The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?

A. Translates virtual addresses to physical addresses

B. Generates parity information to detect soft errors in memory

C. Performs access permission checks

D. Permits the system to be divided into secure and normal worlds, through the use of ARM's TrustZone technology

An external debugger would need to clean the contents of the processor data cache in which of the following cases?

A. When it changes the contents of ARM registers (r0-r15)

B. When it displays the contents of an area of cacheable data

C. When it displays the contents of an area of cacheable code

D. When it sets a software breakpoint

Which of the following ARM processors has a superscalar micro architecture?

A. ARM926EJ-S

B. Cortex-M0

C. Cortex-M3

D. Cortex-A8

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

A. Thumb is a hybrid 16/32-bit instruction set

B. No Thumb instructions can be conditionally executed

C. Thumb code is always slower than the equivalent ARM code

D. Some routines take more instructions in Thumb code than in the equivalent ARM code

E. The Thumb instruction set can access the Advanced SIMD "NEON" instructions

F. Thumb code is always more power-efficient than equivalent ARM code

In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?

A. Copying data from Flash to RAM

B. Changing from one privileged mode to another

C. Loading code into memory and then executing it

D. Incrementing a RAM location that will be read by an interrupt handler